1. Field of the Invention
This invention relates to a semiconductor integrated circuit, particularly to a semiconductor integrated circuit having an internal circuit supplied with a power supply potential and a ground potential and an input circuit or an output circuit.
2. Description of the Related Art
Conventionally, a microcomputer chip has been known as a semiconductor integrated circuit formed of a plurality of internal circuits on a same semiconductor substrate, for example. The microcomputer chip as a semiconductor integrated circuit has a memory circuit such as an arithmetic circuit or a flash memory as an internal circuit, for example.
FIG. 5 is an equivalent circuit diagram showing a semiconductor integrated circuit that formed a basis of this invention. FIG. 6 is a circuit diagram showing a flash memory that is an example of the internal circuit of the semiconductor integrated circuit of FIG. 5.
As shown in FIG. 5, a plurality of internal circuits 1A, 1B, . . . are formed on a semiconductor substrate 200 of the semiconductor integrated circuit. At least one of these internal circuits, for example, the internal circuit 1A is the flash memory as the memory circuit, and the other one of the internal circuits, for example, the internal circuit 1B, is a central processing unit as an arithmetic circuit. These internal circuits 1A and 1B are supplied with a power supply potential Vdd and a ground potential Vss from a power supply terminal Pdd and a ground terminal Pss formed as pad electrodes through a power supply wiring 11 and a ground wiring 21, for example.
Furthermore, an output circuit 31 formed of a P-channel type output transistor MP1 and an N-channel type output transistor MN1 as switching elements is formed on the semiconductor substrate 200. An output terminal P1 formed as a pad electrode for example is connected between the output transistor MP1 and the output transistor MN1. The output circuit 31 outputs an output signal received from the internal circuit or other external circuit from its output terminal P1 as a binary discrete signal.
In a similar manner, an output circuit 32 formed of a P-channel type output transistor MP2 and an N-channel type output transistor MN2 as switching elements is formed on the semiconductor substrate 200. An output terminal P2 formed as a pad electrode for example is connected between the output transistor MP2 and the output transistor MN2. These output circuits 31 and 32 are commonly supplied with a power supply potential Vdd and a ground potential Vss from the power supply terminal Pdd and the ground terminal Pss through a power supply wiring 10 and a ground wiring 20.
However, when noise from outside of the semiconductor integrated circuit is transmitted through the output terminals P1 and P2, the noise is transmitted to the power supply wirings 10 and 11 or the ground wirings 20 and 21 through the output transistors MP1, MN1, MP2, and MN2. With this noise, the power supply potential Vdd or the ground potential Vss fluctuate. The fluctuation of the power supply potential Vdd or the ground potential Vss inverts data in the internal circuits 1A and 1B supplied with the power supply potential Vdd and the ground potential Vss, causing malfunction of the semiconductor integrated circuit.
Hereafter, description will be made on a mechanism of the malfunction when the internal circuit 1A is a flash memory, with reference to a circuit diagram of FIG. 6 showing a structure of a flash memory of the conventional art. FIG. 6 shows main components of the flash memory.
The structure of the flash memory will be described first. As shown in FIG. 6, the internal circuit 1A or the flash memory has a memory cell MC, a reference cell RC, and a readout circuit COMP formed of a comparator supplied with a power supply potential Vdd and a ground potential Vss.
The memory cell MC is formed of a memory transistor MT having a floating gate. The memory transistor MT is stored with “0” or “1” as a storage state corresponding to a charge accumulation state of the floating gate. This storage state is binary data or program data used in an arithmetic circuit and so on. The memory transistor MT is connected with an input terminal of the readout circuit COMP through an output line 61. When this memory transistor MT turns on, in response to its storage state, the potential of the output line 61 is set at a predetermined high level potential or low level potential.
The reference RC is formed of a reference transistor RT having a floating gate, similarly. The reference transistor RT is connected with the power supply potential Vdd and the ground potential Vss and connected with a reference terminal of the readout circuit COMP through a reference line 62.
The readout circuit COMP compares the potentials of the output line 61 and the reference line 62. When the potential of the output line 61 does not exceed the potential of the reference line 62, the readout circuit COMP determines that the storage state of this memory cell is “0”, and outputs a predetermined potential indicating the storage state “0” under the application of the power supply potential Vdd and the ground potential Vss. When the potential of the output line 61 exceeds the potential of the reference line 62, to the contrary, the readout circuit COMP determines that the storage state of this memory cell is “1” and outputs a predetermined potential indicating the storage state “1” under the application of the power supply potential Vdd and the ground potential Vss. These two predetermined potentials are outputted from the output terminal P1 through the output transistors MP1 and MN1 of the output circuit 31 shown in FIG. 5, for example.
At this time, when noise from outside of the semiconductor integrated circuit is transmitted to the inside of the semiconductor integrated circuit through the output terminals P1 and P2 of the output circuits 31 and 32 of FIG. 5, the noise is transmitted to the power supply wirings 10 and 11 or the ground wirings 20 and 21 through the output transistors MP1, MN1, MP2, and MN2 of the output circuits 31 and 32. With this noise, the power supply potential Vdd or the ground potential Vss fluctuates.
In this case, in at least one of the memory cell MC, the reference memory RC, and the readout circuit COMP of the flash memory in FIG. 6 supplied with the power supply voltage Vdd or the ground potential Vss, the storage state is inverted under the influence of the fluctuation of the power supply potential Vdd or the ground potential Vss supplied thereto. This causes an output of a false storage state (i.e. bit inversion), an error in data to be read, and malfunction of the semiconductor integrated circuit (e.g. execution of a different program).
Therefore, as shown in FIG. 5, a noise countermeasure of preventing the influence of the fluctuations of the power supply potential Vdd and the ground potential Vss on the internal circuits 1A and 1B has been provided by connecting the capacitors CA and CB between the power supply wiring 11 and the ground wiring 21 of the internal circuits 1A and 1B.
The relevant technology is described in Japanese Patent Application Publication Nos. 2001-148471, 2004-6691, and Hei. 6-334494.
However, this noise countermeasure in the semiconductor integrated circuit is limited to the internal circuits 1A and 1B. Therefore, even though the noise countermeasure is provided for the internal circuits 1A and 1B, the influence of the fluctuation of the power supply potential Vdd or the ground potential Vss caused by the noise has not been removed properly. As a result, the malfunction of the semiconductor integrated circuit occurs in spite of the noise countermeasure.